Wednesday Keynote Speaker
Fadi Azhari
VP Marketing
Wave Computing
“Meeting the Hyper Growth Challenge of AI Applications”
Fadi Azhari is the VP of Marketing at Wave Computing and plays an integral role in leading go-to-market and product strategy for the company’s deep learning systems. His more than 20 years of experience in the technology industry have helped drive the development of several transformational businesses, including AWS Computer Vision AI services, Nimble Storage Enterprise Adaptive flash storage, and Sun Microsystems SPARC multi-threaded processors and servers. He received a Bachelor of Science degree and Master of Science degree in Electrical Engineering from University of Southern California.
Abstract: Organizations today looking to accelerate their AI and deep learning applications must make significant compromises in performance, price and ease of use due to the limited capabilities of traditional hardware solutions, which only address a narrow set of requirements for very specific needs. For example, they have to use multiple solutions for a single AI application, or they need to use different implementations for different types of data sets. This has created “silos” of different hardware architectures, making the extraction of intelligence from data difficult to manage, provision and scale to meet the hyper growth of AI applications.
In this presentation, Wave Computing VP of Marketing Fadi Azhari will explain how the lack of a common AI platform, from the datacenter to the edge, is slowing AI market growth and reducing the productivity of data scientists in a wide range of fields. He will also explain how Wave Computing is addressing this challenge, and enabling data scientists to experiment, develop, test and deploy neural networks on a common platform spanning to the Edge of Cloud – and enabling enterprise-class companies better leverage AI as a fundamental part of their digital strategies.
Wednesday Plenary Speaker
Vijaykrishnan Narayanan
Distinguished Professor of Computer Science & Engineering and Electrical Engineering
Co-Director of the Microsystems Design Lab
The Pennsylvania State University, USA
“In-Memory Computing: The Resurgence”
Vijaykrishnan Narayanan is Robert Noll Chair of Engineering in Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is a fellow of IEEE and ACM. He leads a NSF Expeditions-in-Computing Center on "Visual Cortex on Silicon" and is a thrust leader for the JUMP Center for Brain-inspired Computing Enabling Autonomous Intelligence. He is an investigator in the NSF ERC ASSIST, NSF/SRC EXCEL Center. Vijay is supported for his in-memory research by the JUMP Center for Research on Intelligent Storage and Processing-in-memory.
Abstract: Compute-in-Memory (CiM) techniques focus on reducing data movement by integrating compute elements within or near the memory primitives. While there have been decades of research on various aspects of such logic and memory integration, the confluence of new technology changes and emerging workloads makes us revisit this design space. This talk focuses on new functionality embedded with SRAMs using emerging monolithic 3D integration. Properties of the new technology transform the costs of embedding such new functionality compared to prior efforts. This work also explores how compute functionality can be embedded into cross-point style non-volatile memory systems. The talk will provide insights into the benefits provided by the proposed technique and evaluate the energy efficiency of the proposed designs.
Thursday Keynote Speaker
Tarek El-Ghazawi
Professor and IEEE Fellow,
The George Washington University, USA
“New Paradigms for Energy-Efficient Computing Beyond the Moore’s Law Era”
Tarek El-Ghazawi is a Professor in the Department of Electrical and Computer Engineering at The George Washington University, where he leads the university-wide Strategic Academic Program in High-Performance Computing. He is a founding director of The GW Institute for Massively Parallel Applications and Computing Technologies (IMPACT) and the NSF Industry/University Center for High-Performance Reconfigurable Computing (CHREC). El-Ghazawi’s research interests include high-performance computing, computer architectures, and heterogeneous computing. He is one of the principal co-authors of the UPC parallel programming language and the first author of the UPC Texbook. El-Ghazawi has published close to 300 refereed research publications in this area. Dr. El-Ghazawi has served in many editorial roles including an Associate Editor for the IEEE Transactions on Computers and Transactions on Parallel and Distributed Systems. He has chaired and co-chaired many international conferences and symposia. Dr. El-Ghazawi’s research has been frequently supported by Federal agencies and industry including DARPA/DoD, NSF, DoE/LBNL, AFRL, NASA, IBM, HP, Intel, AMD, SGI, and Microsoft. Professor El-Ghazawi is a Fellow of the IEEE and was selected Research Faculty Fellow of the IBM Center for Advanced Studies, Toronto. Professor El-Ghazawi was also awarded the Alexander von Humboldt Research Award, and was selected as IEEE Computer Society Distinguished Visor speaker and a UK Royal Academy of Engineering Distinguished Visiting Fellow. He was a recipient of the 2012 Alexander Schwarzkopf Prize for Technical Innovation, and served as a Senior Fulbright Scholar.
Abstract:Due to the end of the Moore’s law in clocking and Dennard’s scaling, we are reaching very crippling limits with our current von Neumann processor paradigms. All the help is sought from both technology and architectures to innovate and engender new processing paradigms that can overcome those limitations and define the future of computing. New ideas and directions ranged from neuromorphic processors, to analog, mersisters, quantum and the use of nano photonics. This talk will examine a number of these emerging directions and work by the community including ours and evaluate some of the associated implications for the future of computing.
Thursday Morning Plenary Speaker
Yu Wang
Associate Professor, E.E. Dept., Tsinghua University, Beijing, China
Co-Founder, Deephi Tech
“Neural Networks on Chip: From CMOS Accelerators to In-Memory-Computing”
Yu Wang received his B.S. degree in 2002 and Ph.D. degree (with honor) in 2007 from Tsinghua University, Beijing. He is currently a Tenured Associate Professor with the Department of Electronic Engineering, Tsinghua University. His research interests include brain inspired computing, application specific hardware computing, parallel circuit analysis, and power/reliability aware system design methodology. Dr. Wang has authored and coauthored over 200 papers in refereed journals and conferences. He has received Best Paper Award in FPGA 2017, NVMSA17, ISVLSI 2012, and Best Poster Award in HEART 2012 with 9 Best Paper Nominations. He is a recipient of DAC Under-40 Innovator Award in 2018 and IBM X10 Faculty Award in 2010. He served as TPC chair for ISVLSI 2018, ICFPT 2011 and Finance Chair of ISLPED 2012-2016, and served as program committee member for leading conferences in these areas, including top EDA conferences such as DAC, DATE, ICCAD, ASP-DAC, and top FPGA conferences such as FPGA and FPT. Currently he serves as Co-EIC for SIGDA E-Newsletter, Associate Editor for IEEE Trans on CAS for Video Technology, IEEE Transactions on CAD, and Journal of Circuits, Systems, and Computers. He also serves as guest editor for Integration, the VLSI Journal and IEEE Transactions on Multi-Scale Computing Systems. He is a recipient of NSF China Excellent Young Scholar, and is now serving as ACM distinguished speaker. He is an IEEE/ACM senior member. He is the co-founder of Deephi Tech (valued over 150M USD), which is a leading deep learning processing platform provider.
Abstract: Artificial neural networks, which dominate artificial intelligence applications such as object recognition and speech recognition, are in evolution. To apply neural networks to wider applications, customized hardware are necessary since CPU and GPU are not efficient enough. Numerous architectures are proposed in the past 4 years to boost the energy efficiency of deep learning inference processing, including Tsinghua and Deephi’s effort. In this talk, we will talk about different architectures based on CMOS technologies, including 200GOPS/W FPGA accelerators, about 1-5TOPS/W chips with DDR subsystems, and over 50TOPs/W chips with everything on chip. The possibilities and trends of adopting emerging NVM technology for efficient learning systems, i.e., in-memory-computing, will also be discussed as one of the most promising ways to improve the energy efficiency.
Thursday Afternoon Plenary Speaker
Krishnendu Chakrabarty
Distinguished Professor and Chair of Electrical and Computer Engineering
Professor of Computer Science
Duke University, USA
“Predictive Analytics for Anomaly Detection and Failure Prediction in Complex Core Routers”
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor and Department Chair of Electrical and Computer Engineering, and Professor of Computer Science, at Duke University. He is also a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany.
Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), and then Semiconductor Research Corporation Technical Excellence Award (2018). He is a recipient of the Japan Society for the Promotion of Science (JSPS) Fellowship in the “Short Term S-Nobel Prize level” category.
Prof. Chakrabarty’s current research projects include: testing and design-for-testability of integrated circuits and systems; microfluidic biochips and cyberphysical systems; data analytics for fault diagnosis, failure prediction, anomaly detection, and hardware security; neuromorphic computing systems. He is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He is a recipient of the 2008 Duke University Graduate School Dean’s Award for excellence in mentoring, and the 2010 Capers and Marion McDonald Award for Excellence in Mentoring and Advising, Pratt School of Engineering, Duke University. He has served as a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016).
Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012 and ACM Journal on Emerging Technologies in Computing Systems during 2010-2015. Currently he serves as the Editor-in-Chief of IEEE Transactions on VLSI Systems.
Abstract: Prognostic diagnosis is desirable for commercial core router systems to ensure early failure prediction and fast error recovery. The effectiveness of prognostic diagnosis depends on whether anomalies can be accurately detected before a failure occurs. However, traditional anomaly detection techniques fail to detect “outliers” when the statistical properties of the monitored data change significantly with time. This talk will describe recent advances in using time-series data analysis to detect anomalies through the real-time monitoring of key performance indicators in core routers. The speaker will describe the design of a changepoint-based anomaly detector ad health-status analyzer that first detects changepoints from collected time-series data, and then utilizes these changepoints to detect anomalies. A clustering method is first used to identify a wide range of normal/abnormal patterns from changepoint windows. Symbolic aggregation approximation and moving-average-based trend approximation are utilized to encode complex time series. Hierarchical agglomerative clustering and sequitur rule discovery are then to learn important global and local patterns. A comprehensive set of experimental results will be presented for data collected during 30 days of field operation from over 20 core routers deployed by customers of a major telecom company.
Banquet Speaker
Sakir Sezer
Chair, Information and Communication Security, Queen's University Belfast, UK
“The Good, the Bad and the Ugly”: An ambitious suicide mission to commercialise academic research via a technology start-up
Sakir Sezer currently holds the Chair of Information and Communication Security at Queen’s University Belfast and is the Director of Research and the Head of the Networked System Security at the Centre for Secure Information Technology (CSIT). Prof. Sezer is a world renowned authority in high-performance network processing and Internet security technologies. His research is leading major advances in the field of high-performance content and security processing, spanning cybersecurity related topics in malware, embedded systems, IoT, ICS and network security. For his achievements Professor Sezer has been awarded a number of prestigious awards including the InvestNI Enterprise Fellowship, and Enterprise Ireland and Intertrade Ireland Innovation and Enterprise awards. Professor Sezer is co-founder and CTO of Titan IC Systems Ltd, and is a member of various research and executive committees.
Abstract: Titan IC, is a University start-up company, established with the mission to commercialise academic research in high-performance content processing. In this talk Prof Sezer will introduce Titan IC and the underpinning technologies based on academic research, targeted technology markets and business engagements with top Silicon Valley companies. The second part of the talk will address challenges faced by the founders in establishing a high-tech start-up dealing with productization of IP, raising funding, developing a successful business model, operations, marketing and customer engagements. The final part of the talk will address “lessons learned” with recommendations for academics and researchers considering a similar technology start-up.
