SOCC 2018 Tutorial Day Program

September 4, 2018

T1A (Room: tbd)

Thermal- and Reliability-Aware Design in Nanometer Technologies
Mircea Stan, Professor and Chair of High-Performance Low-Power (HPLP) lab, University of Virginia

Biography: Mircea R. Stan received the Ph.D. (1996) and the M.S. (1994) degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from the Polytechnic Institute in Bucharest, Romania. Since 1996 he has been with the Charles L. Brown Department of ECE at the University of Virginia, where he is now a professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, spintronics, and nanoelectronics.

He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). He has more than eight years of industrial experience, has been a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999.

He has received the NSF CAREER award in 1997 and was a co-author on best paper awards at SELSE 2017, ISQED 2008, GLSVLSI 2006, ISCA 2003 and SHAMAN 2002. He gave conference keynotes at SOCC 2016, CNNA 2014, WoNDP 2015 and iNIS 2015. He was the chair of the VSA-TC of IEEE CAS in 2005-2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for ISVLSI 2017, NanoNets 2007 and ISLPED 2005, and on technical committees for numerous conferences. He is a Senior Editor for the IEEE Transactions on Nanotechnology and an AE for IEEE Design & Test since 2014, and was an AE for the IEEE TNano in 2012-2014, IEEE TCAS I in 2004-2008 and for the IEEE TVLSI in 2001-2003. He was Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society in 2012-2013 and 2004-2005, and for the Solid-State Circuits Society (SSCS) in 2007-2008. Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.

T1B (Room: tbd)

The Good, The Bad, and The Potential, A Tutorial for the Adversarial Attacks
Xiang Chen, Assistant Professor, George Mason University

Abstract: With Deep Neural Network (DNN) as the most representative technology, the machine learning has the been widely applied in to daily applications, However, with the fast-growth of machine learning technology and DNN equipped applications, a new DNN attack method – adversarial attack has demonstrated considerable negative impact to the machine learning development. The adversarial attack is derived from the DNN model structure to manipulate the classification result by crafting dedicated perturbations on the original images, that even human vision can’t perceive. Recently many research works are focusing on the adversarial attack generation and defense.
In this tutorial, we will introduce the fundamental generation and defense approaches for the adversarial attacks. To illustrate the impact of the adversarial attacks, we will give interactive instructions to generate and defense the adversarial examples embodied by images and audios. Moreover, we reveal how the nature of adversarial example generation and how it can guide the neural network design and optimization to benefit networks’ robustness, transferability and generality.

Biography: Dr. Xiang Chen is an Assistant Professor in the Department of Electrical and Computer Engineering (ECE) in the George Mason University. He received his Ph.D. and M.S. degrees from the Computer Engineering in 2016 and 2012 from the University of Pittsburgh. He earned his B.S. degrees from the Northeastern University. Before joining the George Mason University, he used to work with the Samsung Research Lab and Microsoft Research Asia. His research focuses on the areas of high-performance computing system and system security. Currently, his is focusing on the hardware-software co-design for modern mobile computing systems with emphasis on the deep learning technologies. Dr. Chen received the best paper nominations from ICCAD 2016 and the best paper award from DATE 2017.

T1C (Room: tbd)

IoT Security: - Threats, Security Challenges and IoT Security Research and Technology Trends
Sakir Sezer, Chair, Information and Communication Security, Queen's University Belfast, UK

Abstract: Internet of Things (IoT) defines the foundation for interconnecting any device that will benefit to be interconnected to control or collect instant information of anything and everything. It is considered to be the fabric of future Smart Cities, Smart Homes, Smart Utilities, Smart Transport and Connected Health. Such emerging technologies and services bear significant economic and social benefits, but when misused pose serious risks and threats to individuals, business and societies. The talk will discuss various IoT security threats and privacy related security challenges due to the vulnerabilities of embedded systems and the underpinning communication and silicon technologies, and will give an overview of emerging IoT security technologies and state-of-the-art IoT security research trends.

Biography: Sakir Sezer currently holds the Chair of Information and Communication Security at Queen’s University Belfast and is the Director of Research and the Head of the Networked System Security at the Centre for Secure Information Technology (CSIT). Prof. Sezer is a world renowned authority in high-performance network processing and Internet security technologies. His research is leading major advances in the field of high-performance content and security processing, spanning cybersecurity related topics in malware, embedded systems, IoT, ICS and network security. For his achievements Professor Sezer has been awarded a number of prestigious awards including the InvestNI Enterprise Fellowship, and Enterprise Ireland and Intertrade Ireland Innovation and Enterprise awards. Professor Sezer is co-founder and CTO of Titan IC Systems Ltd, and is a member of various research and executive committees.

T2A (Room: tbd)

Benchmarking of Advanced CMOS and beyond CMOS circuits
Andrew Marshall, Research Professor, University of Texas, Dallas

Abstract: Benchmarking and performance closure have increased in importance since the early development of ICs, and with continued feature size shrinkage has become more significant than ever. The aim of this tutorial is to explain the history of benchmarking, beginning with CMOS logic, and describing the evolution of changes and additions to the methodology as CMOS density has increased.
As it has become physically more difficult and more expensive to extend the performance characteristics of planar CMOS technology, there have been many efforts to create new technologies. Some of these are CMOS extensions, such as Finfet devices. Others are the so-called beyond CMOS devices, which include charge-based logic such as Tunnel FET based systems, others are non-charge based, which include nano-magnetic structures, spintronics devices, advanced charge-based devices and a variety of quantum structures.
All these need to be benchmarked and evaluated against each other, as it is important to determine which of these technologies offer advantages over conventional CMOS. Therefore there has developed a need for comparative benchmarking across logic families. We here detail benchmarking of CMOS and of newer beyond CMOS technologies, and consider how the benchmarking standards have changed by the addition of beyond CMOS capability.

Biography: Andrew Marshall is an analog and digital IC design expert, working on benchmarking of leading edge and future technologies. He is a research professor at the University of Texas in Dallas. Dr. Marshall has authored/co-authored approximately 85 patents and 100 papers. He is co-author of the book ‘SOI Design: Analog, Memory and Digital Techniques’ and sole author of “Mismatch and Noise in Modern IC Processes”. Dr. Marshall is a Fellow of both the IEEE and Institute of Physics, and Fellow Emeritus of Texas Instruments Incorporated.

T2B (Room: tbd)

Ultra-Low Power System Optimization & Energy Harvesting Opportunities
Brian Zahnstecher, Principal, PowerRox and Chair, IEEE Power Electronics Society

Abstract: Integration of electronics into system-on-chip solutions means a lot of things. It means finding ways to shrink and incorporate passives into existing substrates, typically enabled by increasing the switching frequency of power converters. It means finding the best opportunities for aggregation of some system aspects, while disaggregating and optimizing others. Most importantly, it means reducing the overall power consumption of a system for a given application. Whether the system be an offline-powered solution (i.e. – bulk power supply, adapter, etc.) or a portable solution (i.e. – battery), the power source is typically a dominant component in the overall form-factor of the system as well as the limiting factor in operating life and/or feature set.

When it comes to the tens of billions or even trillions of Internet of Things (IoT) devices that are predicted to dominate every aspect of our personal and professional lives only a few years from now,
ultra-low power devices are sure to make up the far majority. Whether it be 5G edge user equipment like smartphones or ubiquitously deployed Bluetooth Low Energy (BLE) beacons and wireless sensor networks (WSN), the optimization of power budgets <<1W is essential to enabling the fantastic marketing projections before us. Combining intelligent power management (IPM) techniques with the array of technological advances that allow us to do so much with so little power these days, there is another key opportunity that has been enabled by these technologies. We now have the ability to supplement a system power source or even completely replace with energy harvesting (EH) sources. This means powering a system from energy scavenged from the ambient environment.

In the past, EH has been dismissed as providing negligible power and/or an academic experiment not ready for production, consumer applications. This tutorial not only intends to quickly diminish these common misperceptions, but go further to demonstrate the value (in technical, monetary, and global terms) EH brings to ultra-low power applications and show how such a marriage of technologies is not merely enabling, but actually essential to making a reality out of all the marketing projections. First, we will dive into the strategies behind what goes into a system power budget and identify the key opportunities for power savings and overall reduction of the budget via IPM techniques. Then, we will give a comprehensive overview of what EH is and how the various transducers, power management integrated circuits (PMIC), energy storage, and individual applications allow us to yield usable power from every form of energy physics affords us.

Finally, the tutorial will conclude with a series of case studies and real-world examples that demonstrate the path from the constituents of the production EH ecosystem existing today to empowering the deployment of a variety of IoT and other notable solutions. These examples shall speak to a wide range of markets and verticals including, but not limited to IoT (inc. industrial IoT or IIoT), wearables, WSN, medical, autonomous vehicles, factory automation, 5G, environmental monitoring, system management, and more. The tutorial is intended for Design Engineers, Device Architects, System Implementers, Program Managers, & Technical Marketing/Sales Personnel associated with optimizing and enabling ultra-low power products/applications/industries.

Biography: Brian Zahnstecher is a Sr. Member of the IEEE, Chair of the IEEE SFBAC Power Electronics Society (PELS) awarded 2017 Best Chapter awards at the local/national/worldwide levels concurrently (an unprecedented achievement), sits on the Power Sources Manufacturers Association (PSMA) Board of Directors, and is the Principal of PowerRox, where he focuses on power design, integration, system applications, OEM market penetration, market research/analysis, and private seminars for power electronics. He leads Power for the IEEE 5G Roadmap Applications & Services Working Group, authored the Group’s position paper, and has lectured on this topic at major industry conferences. He has successfully handled assignments in system design/architecting, AC/DC front-end power, EMC/EMI design/debug, embedded solutions, processor power, and digital power solutions for a variety of clients. He previously held positions in power electronics with industry leaders Emerson Network Power (now Artesyn), Cisco, and Hewlett-Packard, where he advised on best practices, oversaw product development, managed international teams, created/enhanced optimal workflows and test procedures, and designed and optimized voltage regulators. He has been a regular contributor to the industry as an invited keynote speaker, author, workshop participant, session host, roundtable moderator, and volunteer. He has over 14 years of industry experience and holds Master of Engineering and Bachelor of Science degrees from Worcester Polytechnic Institute.